The present invention relates generally to very-large-scale integration (VLSI) devices, and relates more particularly to predicting the yield of VLSI chips.
Critical area is a measure of the sensitivity of a VLSI chip design to random particle defects and is widely used to predict the yield of a VLSI chip in the presence such defects. For example, extra material defects may cause shorts (short circuits) between different conducting regions, while missing material defects may cause opens (open circuits). The latter case occurs when a conducting path is broken into two or more pieces. To reduce the occurrence of opens, many VLSI chip designers insert redundant interconnects (loops) in their designs. These loops provide alternate routes that allow a circuit to remain connected in the presence of defects that might otherwise cause an open. At the same time, however, the loops increase the potential for shorts. Accurate critical area computation is essential in balancing these competing concerns.
Accurate and efficient computation of critical area is therefore very important in integrated circuit (IC) manufacturing, especially when design for manufacturability (DFM) initiatives are a consideration. Conventional tools for computing critical area, however, fail to account for the loops described above, and thereby overestimate the actual critical area for opens while (correctly) registering an increase in critical area for shorts. This is because these tools assume that interconnects are routed in a tree fashion, and thus any defect that breaks any conducting path is assumed to create an open. As a result, designs incorporating loops are erroneously penalized.
Thus, there is a need in the art for a method and apparatus for net-aware critical area extraction.